? semiconductor components industries, llc, 2012 april, 2012 ? rev. 0 1 publication order number: NB3N15552MN/d nb3nxxxxx - vcxo series 3.3v pureedge vcxo clock generator with differential lvpecl outputs description the nb3nxxxxx ? series voltage ? controlled crystal oscillator (vcxo) devices are designed to meet today?s requirements for 3.3 v lvpecl clock generation applications. these devices use an external high q fundamental mode pullable crystal and phase locked loop (pll) multiplier to provide a wide range of frequencies from 60 mhz to 700 mhz (factory configurable per user specifications) with a pullable range of 100 ppm. the silicon ? based pureedge products provides users with exceptional frequency stability and reliability. they produce an ultra low jitter and phase noise l vpecl differential output. the nb3nxxxxx ? series are members of on semiconductor?s pureedge clock family that provides accurate and precision clock generation solutions. available in the industry standard 4 mm x 4 mm qfn ? 20 package. features ? lvpecl differential output ? operating range: 3.3 v 10% ? ultra low jitter and phase noise ? 0.5 ps (12 khz ? 20 mhz) ? 245 ps typical rise and fall times ? factory configurable frequencies from 60 mhz to 700 mhz (see standard frequencies in the ordering information table in page 5) ? pullable range minimum of 100 ppm ? control voltage with positive slope ? ? 40 c to +85 c ambient operating temperature ? these devices are pb ? free and are rohs compliant applications ? networking ? sonet ? 10 gigabit ethernet ? networking base stations ? broadcasting marking diagram *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information http://onsemi.com (*note: microdot may be in either location) qfn20 mn suffix case 485e xxxxx = frequency xxx.xx a = assembly location l, wl = wafer lot y = year w, ww = work week g or = pb ? free package nb3n xxxxx alyw 1 20 figure 1. simplified block diagram of nb3nxxxxx v dd clk clk gnd oe v c xin xout pll clock multiplier
nb3nxxxxx ? vcxo series http://onsemi.com 2 1 2 3 4 5 15 14 13 12 11 678910 20 19 18 17 16 figure 2. qfn ? 20 pinout (top view) nc v dd v dd xin xout nc v dd clk nc clk nc gnd oe gnd nc v c gnd nc nc nc exposed pad table 1. output enable tri ? state function oe output pins function open active high active low high z table 2. pin description pin name i/o description 1 vc analog input analog control voltage input pin that adjusts output oscillation frequency. f0 = v c = 1.65 v. control voltage has a positive slope with a linearity of 10%; v c = 1.65 v 1 v. 2 oe lvttl / lvcmos input output enable pin. when left floating pin defaults to logic high and output is active. see oe pin description table 1. 3 gnd ground negative supply voltage 4 gnd ground negative supply voltage 5 gnd ground negative supply voltage 6 nc no connect 7 nc no connect 8 nc no connect 9 nc no connect 10 nc no connect 11 clk lvpecl output non ? inverted differential output. typically terminated with 50 resistor to v dd ? 2 v. 12 clk lvpecl output inverted differential output. typically terminated with 50 resistor to v dd ? 2 v. 13 vdd power supply 3.3 v positive supply voltage 14 vdd power supply 3.3 v positive supply voltage 15 vdd power supply 3.3 v positive supply voltage 16 nc no connect 17 xout crystal crystal input. this pin forms an oscillator when connected to an external parallel ? resonant crystal. 18 nc no connect 19 xin crystal crystal input. this pin forms an oscillator when connected to an external parallel ? resonant crystal.
nb3nxxxxx ? vcxo series http://onsemi.com 3 table 2. pin description pin description i/o name 20 nc no connect ? ep the exposed pad (ep) on the qfn ? 20 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is electrically connected to the die, and must be electrically and thermally connected to gnd on the pc board. 1. all vdd and gnd pins must be externally connected to a power supply for proper operation. table 3. attributes characteristics value internal default state resistor (oe) 170 k esd protection human body model machine model 2 kv 200 v moisture sensitivity, indefinite time out of drypack (note 2) level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 3510 devices meets or exceeds jedec standard eia/jesd78 ic latchup test 2. for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 1 rating unit v dd positive power supply gnd = 0 v 4.6 v v in control input (v c and oe) v in v dd + 200 mv v in gnd ? 200 mv v i out lvpecl output current continuous surge 25 50 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 55 to +120 c ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm qfn ? 20 qfn ? 20 47 33 c/w jc thermal resistance (junction ? to ? case) (note 3) standard board qfn ? 20 18 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad. table 5. recommended crystal parameters crystal type fundamental at ? cut frequency various ? device dependent; see ac table load capacitance 16 pf shunt capacitance, c0 3.2 pf typical motional capacitance (c1) 12 ff typical capacitance ratio (c0/c1) 260 typical esr (equivalent series resistance) 25 max; 5 typical
nb3nxxxxx ? vcxo series http://onsemi.com 4 table 6. dc characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) (note 4) symbol characteristic min typ max unit idd power supply current 90 110 ma vih input high voltage, oe 2000 v dd mv vil input low voltage, oe gnd ? 200 800 mv iih input high current, oe ? 100 +100 ua iil input low current, oe ? 100 +100 ua voh output high voltage v dd ? 1195 v dd ? 945 mv vol output low voltage v dd ? 1945 v dd ? 1600 mv voutpp output voltage amplitude 700 mv 4. measurement taken with outputs terminated with 50 to v dd ? 2.0 v. see figure 3. table 7. ac characteristics (v dd = 3.3 10%, gnd = 0 v, t a = ? 40 c to +85 c) symbol characteristic conditions min typ max unit f clkout output clock frequency crystal fref = 28.276363 mhz nb3n15552 155.52 mhz crystal fref = 28.409090 mhz nb3n15625 156.25 crystal fref = 30.703125 mhz nb3n49152 491.52 crystal fref = 28.276363 mhz nb3n62208 622.08 t jit(cp) rms phase jitter 12 khz to 20 mhz 0.5 0.9 ps t jitter cycle to cycle, rms 1000 cycles 2 8 ps cycle to cycle, peak ? to ? peak 1000 cycles 10 30 period, rms 10,000 cycles 1 4 period, peak ? to ? peak 10,000 cycles 6 20 t oe/od output enable/disable time 200 ns f p crystal pull ability (note 5) 0 v c 3.3 v 100 ppm v c(bw) control voltage bandwidth ? 3 db 20 khz t duty_cycle output clock duty cycle (measured at cross point) 45 50 55 % t r output rise time (20% and 80%) 245 400 ps t f output fall time (80% and 20%) 245 400 ps t start start ? up time 1 5 ms 5. gain transfer is positive with a rate of 130 ppm/v. table 8. phase noise performance parameter characteristic condition 155.52 mhz 156.25 mhz 491.52 mhz 622.08 mhz unit noise output phase - noise performance 100 hz offset ? 82 ? 82 ? 72 ? 70 dbc/hz 1 khz offset ? 106 ? 106 ? 96 ? 94 dbc/hz 10 khz offset ? 126 ? 126 ? 11 6 ? 11 4 dbc/hz 100 khz offset ? 128 ? 128 ? 11 9 ? 11 6 dbc/hz 1 mhz offset ? 135 ? 135 ? 125 ? 123 dbc/hz 10 mhz offset ? 159 ? 159 ? 151 ? 149 dbc/hz
nb3nxxxxx ? vcxo series http://onsemi.com 5 ordering information device frequency (mhz) package shipping ? NB3N15552MNg 155.52 qfn ? 20 (pb ? free) 92 units / rail NB3N15552MNtxg 155.52 qfn ? 20 (pb ? free) 3000 / tape & reel nb3n15625mng 156.25 qfn ? 20 (pb ? free) 92 units / rail nb3n15625mntxg 156.25 qfn ? 20 (pb ? free) 3000 / tape & reel nb3n49152mng 491.52 qfn ? 20 (pb ? free) 92 units / rail nb3n49152mntxg 491.52 qfn ? 20 (pb ? free) 3000 / tape & reel nb3n62208mng 622.08 qfn ? 20 (pb ? free) 92 units / rail nb3n62208mntxg 622.08 qfn ? 20 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. figure 3. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v dd ? 2.0 v nb3nxxxxx
nb3nxxxxx ? vcxo series http://onsemi.com 6 package dimensions case 485e ? 01 issue b 2.88 20x 0.35 20x 0.58 4.30 0.50 dimensions: millimeters 1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* pitch pkg outline dim min max millimeters d 4.00 bsc e 4.00 bsc a 0.80 1.00 b 0.20 0.30 e 0.50 bsc l1 0.00 0.15 a3 0.20 ref a1 --- 0.05 l 0.35 0.45 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. d2 e2 1 6 11 20 d2 2.60 2.90 e2 2.60 2.90 e l1 detail a l optional constructions ?? ?? ?? 0.15 c pin one reference top view 2x 0.15 c a a1 (a3) 0.08 c 0.10 c c seating plane side view detail b bottom view b 20x 0.10 b 0.05 a c c note 3 detail a k 0.20 ref 0.10 b a c l 20x 0.10 b a c k 4.30 2.88 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NB3N15552MN/d pureedge is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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